The present invention relates to an ultrasonic transducer driving circuit and an ultrasonic diagnostic apparatus and, more particularly, relates to an ultrasonic transducer driving circuit and an ultrasonic diagnostic apparatus that can suppress power consumption and allow for a reduction in circuit size.
Heretofore, there is known an ultrasonic diagnostic apparatus including a positive FET (Field Effect Transistor) which outputs a positive voltage onto an output line to an ultrasonic transducer at on state, a negative FET which outputs a negative voltage onto the output line to the ultrasonic transducer, and a driver circuit which drives the positive FET and the negative FET (e.g., see Patent Document 1 and Patent Document 2).
[Patent Document 1] Japanese Unexamined Patent Publication No. 2006-101997 (FIG. 10, FIG. 12, FIG. 14)
[Patent Document 2] Japanese Unexamined Patent Publication No. 2004-358133 (FIG. 2)
In the above ultrasonic diagnostic apparatus of prior art, the output voltage to the ultrasonic transducer can be controlled by adjusting the gate voltages of the FETs (adjusting the voltage drop across each FET).
However, each FET remains on as long as a pulse width duration when a pulse of a voltage is applied to the ultrasonic transducer and this posed a problem of an increase in power consumption.
For this reason, in the above ultrasonic diagnostic apparatus of prior art, power consumption is suppressed by switching the supply voltage to each FET to a low voltage (to reduce the voltage drop across the FET) when the output voltage to the ultrasonic transducer is low.
However, since a supply voltage switching circuit for each FET is a power supply circuit, a problem that the circuit size becomes larger emerged.